The present invention relates generally to audio frequency clock generation systems, especially for use in audio DAC systems which can replay digital audio data in analog format, for example by decoding it from compressed MP3 format or by receiving it in PCM (pulse code modulation) format supplied by a digital signal processor (DSP).
Audio digital to analog converters (DACs) are widely used in various applications, such as cell phones and MP3 players, wherein the digital audio samples are played back by means of speakers and/or headphones. Because audio signals are typically are stored and processed in digital format, the number of applications of audio DACs are increasing. Normally, a digital signal processor performs a decoding if the original audio data are compressed, and then processes and transfers the decoded and processed audio data to the audio DAC continuously at the audio data sampling rate. The audio DAC receives the audio data and plays it at a rate derived from the externally provided operating clock rate. Typically, the operating clock rate is 512, 256 or 128 times the audio sampling rate.
Since audio signals typically are presented in one of several digital formats, digital and mixed digital/analog audio converting and processing circuits are widely used. High frequency clocks (e.g., tens of MHz) are essential to enable those digital and mixed digital/analog circuits to operate. In many cases, the operating clock frequencies are required to be exponential multiples (i.e., powers of 2) of the audio sampling rates of the digital and mixed digital/analog audio converting and processing circuits.
There are two ways to reproduce digital speech and audio data. One way is to use a sample rate converter, as described in the assignee's U.S. Pat. No. 7,262,716 issued Aug. 20, 2007 and U.S. Pat. No. 7,408,485 issued Aug. 5, 2008. Another way is to play back the digital audio data with the clock synchronized to, or with the clock output sampling rate the same as, the input sampling rate used when the digital audio speech and audio data was recorded. In that case a sample rate converter is not needed, and it is necessary to generate an output sample rate clock having a frequency which is proportional to the input sample rate at which the original audio data was recorded. This is generally accomplished by using an external reference clock and a PLL to multiply that reference clock either by an integer or by a fractional number in order to generate an output clock signal having the needed output audio sampling frequency proportional to the original input sample rate. But if the reference clock is too slow for the PLL, it is likely to become unstable.
There are several ways of generating such clock signals. One way is to use a crystal oscillator which generates a fixed-frequency clock signal. One main advantages of using a crystal oscillator is that the clock signals based thereon tend to have low jitter. Another advantage is that no external reference clock signal is needed. However, a disadvantage of using a crystal oscillator is that the clock signal frequency is fixed, whereas an adjustable-frequency clock signal may be needed.
As previously indicated, another way of generating clock signals of the desired frequency for digital and mixed digital/analog circuits is to use a phase locked loop (PLL) and an external reference clock signal to generate a clock of the desired frequency. A PLL has a particular “tuning range” within which the frequency of the reference clock can be adjusted. However, the PLL performance deteriorates when the reference clock frequency is outside of its tuning range, especially for a reference clock frequency below roughly 1 kHz, to a point at which the PLL can not function normally. The performance deterioration referred to may include increased clock jitter and “wobble” of the clock frequency as the jitter becomes worse.
A clock filtering and clock divide ratio estimator circuit which is shown in subsequently described “Prior Art” FIG. 2A is similar to the loop filter 71 in FIG. 4A of the assignee's U.S. Pat. No. 7,408,485 entitled “ASYNCHRONOUS SAMPLING RATE CONVERTER AND METHOD FOR AUDIO DAC”, issued on Aug. 5, 2008, and incorporated herein by reference. Further details of a similar loop filter are shown in FIG. 2 of the assignee's U.S. Pat. No. 7,262,716, entitled “ASYNCHRONOUS SAMPLE RATE CONVERTER AND METHOD”, issued Aug. 20, 2007, and also incorporated herein by reference.
There is an unmet need for a low jitter clock signal generating system which produces a high frequency clock signal based on a relatively low frequency reference clock signal.
There also is an unmet need for a clock signal generating system which produces an adjustable high frequency, low jitter clock signal based on a relatively low frequency reference clock signal.
There also is an unmet need for a clock signal generating system which does not utilize a sample rate converter and which produces an adjustable high frequency, low jitter clock signal based on a relatively low frequency reference clock signal and a phase locked loop (PLL).
There also is an unmet need for a clock signal generating system which does not utilize a sample rate converter and which produces an adjustable high frequency, low jitter clock signal based on a relatively low frequency reference clock signal and a phase locked loop (PLL), wherein the phase of the adjustable high frequency, low jitter clock signal is locked relative to the phase of the low frequency reference clock signal.
There also is an unmet need for a clock signal generating system which can generate high frequency clock signals with fine granularity frequency adjustment for a wide range of low reference clock frequencies.